1. Field of the Invention
The present invention relates to a memory device, and more particularly to a single-ended bit line structure of latched type, capable of sensing data at a high speed.
2. Description of Prior Art
In general, the single-ended bit line structure is adapted to a multi-port SRAM, a ROM, a PLA and the like. The single-ended bit line structure amplifies and senses the voltage difference between a referenced bit line and a bit line coupled to the cell in which data is stored. This single-ended bit line structure has been used for a low speed and has employed a simplified differential amplifier.
However, the chip for a high speed and a low power consumption is needed. In particular, with the increase of the speed of the microprocessor, it has been very important to design the architecture of the memory device operating at low power consumption.
FIG. 1 is a block diagram illustrating a ROM having a conventional single-ended sense amplifier.
Referring to FIG. 1, the conventional single-ended sense amplifier includes a differential sense amplifier 10 which senses the voltage difference between a reference voltage from a reference voltage generator 20 and the bit lie voltage and then amplifies it. The reference voltage generator 20 provides a low voltage, for example, the threshold voltage caused by the diode connection of a PMOS and NMOS transistors, to the differential sense amplifier 10 such that the differential sense amplifier 10 senses data stored in the memory cell.
On the other hand, to decrease the power consumption of the differential sense amplifier, the sense enable clock signal to enable the differential sense amplifier must be generated after the voltage on the bit line is enough higher or lower than the reference voltage. Accordingly, it is impossible for the conventional single-ended sense amplifier to operate at a high speed and in a low voltage.